Half Adder Virtual Laboratory

PrayogSetu — Interactive Digital Electronics Lab
Experiment
🎛️ Input Controls
Input A
Input B
⚡ Half Adder Logic Circuit
A 0 B 0 XOR AND SUM 0 CARRY 0 SUM = A ⊕ B (XOR) | CARRY = A · B (AND)
📊 Output Display
SUM (A ⊕ B)
0
LOW
CARRY (A · B)
0
LOW
✓ HALF ADDER OUTPUT VERIFIED
📋 Half Adder Truth Table
A B SUM (A ⊕ B) CARRY (A · B)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
📖 Working Principle — Half Adder

What is a Half Adder?

A Half Adder is the most fundamental combinational logic circuit used for binary addition. It adds two single-bit binary numbers and produces two outputs: SUM and CARRY. It is called a "half" adder because it does not account for a carry input from a previous stage — it can only add two bits, not three.

How Binary Addition Works

In binary arithmetic, addition follows the same principle as decimal addition, but with only two digits: 0 and 1.

  • 0 + 0 = 0 — No sum, no carry.
  • 0 + 1 = 1 — Sum is 1, no carry.
  • 1 + 0 = 1 — Sum is 1, no carry.
  • 1 + 1 = 10 — Sum is 0 (written in the current bit), carry is 1 (passed to the next higher bit position).

The Half Adder implements exactly this behavior using two logic gates.

Role of the XOR Gate — Generating SUM

SUM = A ⊕ B

The Exclusive OR (XOR) gate outputs HIGH (1) when exactly one of its inputs is HIGH. This perfectly models the sum digit of binary addition: the sum is 1 only when the two input bits differ, and 0 when they are the same.

Role of the AND Gate — Generating CARRY

CARRY = A · B

The AND gate outputs HIGH (1) only when both inputs are HIGH. In binary addition, a carry is generated only when both bits being added are 1 (since 1 + 1 = 10 in binary). The AND gate detects exactly this condition.

Difference Between SUM and CARRY

  • SUM represents the least significant bit (LSB) of the addition result. It is the bit written in the current position.
  • CARRY represents the bit that overflows to the next higher position, similar to "carrying the 1" in decimal addition.

Together, SUM and CARRY give the complete 2-bit result of adding two single-bit numbers.

Why the Half Adder Has No Carry-In

The Half Adder is designed to add only the least significant bits of a binary number. At the LSB position, there is no previous stage that could produce a carry, so a carry-in input is not needed. When multi-bit addition is required, a Full Adder is used — it accepts three inputs (A, B, and Carry-In) and can be cascaded to add numbers of any width. A Full Adder is essentially built from two Half Adders and an OR gate.

🧪 Experiment Observation
Ready — Toggle inputs or run automatic test
# A B Expected SUM Actual SUM Expected CARRY Actual CARRY Status
1 0 0 0 — 0 — Pending
2 0 1 1 — 0 — Pending
3 1 0 1 — 0 — Pending
4 1 1 0 — 1 — Pending